1. Field of the Invention
The present invention relates to programming non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded, causing electrons from the channel of a cell or memory element, e.g., storage element, to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element is raised so that the memory element is in a programmed state. More information about such programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory,” and in U.S. Patent Application Publication 2005/0024939, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003; both of which are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, the program voltage applied to the control gate during a program operation is applied as a series of pulses. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2–0.4 V. FIG. 1 shows a program voltage signal Vpgm that can be applied to the control gates (or, in some cases, steering gates) of flash memory elements. Vpgm includes a series of pulses that increase in magnitude over time. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed. For arrays of multi-state flash memory elements, a verification step may be performed for each state of an element to allow a determination of whether the element has reached its data-associated verify level. For example, a multi-state memory element capable of storing data in four states may need to perform verify operations for three compare points.
If an element does not reach the desired program level after a given number of pulses, which is conventionally fixed, an error condition is declared. The choice of the magnitude of program voltage Vpgm, including an initial value, the voltage step size, if applicable, and the maximum number of pulses to apply before declaring an error condition, involves a compromise among various factors. In particular, if the initial value or the step size is too large, some memory elements may be over-programmed, resulting in an inaccurate threshold voltage, while longer programming times will result if the initial value or the step size is too small. Typically, users of non-volatile memory desire that the memory program quickly. Furthermore, the number of pulses needed to program different memory elements to a desired state can differ. Slower memory elements will need more pulses while faster memory elements will need fewer pulses. In order to have a sufficient margin or cushion so that the die-sort yield is acceptable, a relatively large number of Vpgm pulses is typically allowed. For example, in 90 nm devices, although most upper pages in multi-state memory element devices can be programmed within eighteen pulses, the maximum allowed number of pulses may be set at, e.g., twenty-four, to provide a margin of six pulses. However, if one normal page of memory elements has several slow elements or has one bad column, the entire page will keep programming until the maximum number of pulses has occurred.
As a result, some elements along the same word line as the slow element or the bad column could be disturbed. Moreover, this scenario is more severe for cycled devices, which have undergone many programming cycles, than for fresh devices, which have not been significantly used, because the cycled devices are faster than fresh devices due to charge trapping. In particular, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulator or dielectric between the floating gate and the channel region. This trapping of charge shifts the threshold voltage to a higher level, which allows the memory element to program quicker while also making it harder to erase the charge in the element. If the magnitude of the program signal is set too high, even though it does not result in over programming of a fresh device, as that device becomes more heavily used, that device may experience over programming. Thus, new devices will have their program voltage set low enough to avoid over programming when the device is older. This lowering of the magnitude of the program voltage will reduce the speed at which the fresh device programs data.
Consequently, an excessive number of program pulses may be applied to the normal elements in the cycled device. The problem is exacerbated by the fact that cycled devices have more bad columns than fresh devices. While it is possible to lower the number of Vpgm pulses used before declaring an error condition, as mentioned, this reduces yield. For example, if the maximum number of program pulses is reduced from twenty-four to twenty-two, the die-sort yield is reduced by about 5%, which is generally considered to be unacceptable.